The present invention relates to a semiconductor memory device and a technology for improving a noise margin and an operating speed of an SRAM (Static Random Access Memory) and achieving low power consumption thereof, e.g., a technology effective for application to an SRAM having CMOS flip-flop circuit type memory cells or an LSI (Large Scale Integration) with the SRAM built therein.
In a semiconductor memory device (hereinafter called a xe2x80x9csemiconductor memoryxe2x80x9d or simply xe2x80x9cmemoryxe2x80x9d) such as an SRAM, an increase in capacity has been put forward with the scale-down of an elemental device by a process. On the other hand, when process-based scale-down is effected according to a so-called scaling law in a semiconductor memory comprising MOSFETs, a gate insulating film for MOSFETs constituting a memory cell and a peripheral circuit becomes thin. Therefore, a withstand voltage of each MOSFET becomes low with the scale-down. In a semiconductor integrated circuit, the lower a source or power supply voltage, the less its power consumption. Further, as the MOSFET becomes low in threshold voltage, the semiconductor integrated circuit can perform a high-speed operation. Therefore, a reduction in power supply voltage has been carried out with the scale-down.
Meanwhile, when a threshold voltage of each MOSFET that constitutes a memory cell, is reduced or a source or power supply voltage for the memory cell is lowered in the SRAM, a defective condition takes place in that a leak current increases and a static noise margin is reduced, and a so-called soft error in which memory information is reversed due to an a ray, is apt to occur.
There has heretofore been proposed an invention wherein in order to prevent an increase in leak current due to a reduction in threshold voltage of each MOSFET constituting a memory cell and improve an operating speed, the threshold voltage of each MOSFET constituting the memory cell is set high and the threshold voltage of each MOSFET constituting a peripheral circuit is reduced (e.g., see Unexamined Patent Publication No. Hei 3(1991)-83289). There has also been proposed an invention wherein in order to reduce power consumption while the speeding-up of read and write operations is being carried out, a source or power supply voltage for each memory cell is set high and the threshold voltage of each MOSFET that constitutes the memory cell, is set high, whereas a power supply voltage for a peripheral circuit is reduced (e.g., see Unexamined Patent Publication No. Hei 10(1998)-242839 (corresponding U.S. Pat. No. 6,046,627), and Unexamined Patent Publication No. Hei 9(1997)-185886 (corresponding U.S. Pat. No. 5,757,702)).
However, while each of the above references discloses that the threshold voltage of each MOSFET constituting the memory cell and its power supply voltage are set higher than those for the peripheral circuit but does not disclose how to cope with a potential on each word line, a gate size of each MOSFET constituting the memory cell, the thickness of an insulating film, etc. Therefore, the present inventors have found out that improvements in noise margin and read rate and reductions in power consumption and cell area have not yet been achieved sufficiently.
Described specifically, when the threshold voltage of each MOSFET constituting the memory cell is set higher than that for the peripheral circuit as in the invention of the prior application (Unexamined Patent Publication No. Hei 3(1991)-83289), the memory cell cannot be operated at high speed like the peripheral circuit, thereby causing a defective condition that the read rate cannot be made fast. As in the inventions disclosed in Unexamined Patent Publication Nos. Hei 10(1998)-242839 and Hei 9(1997)-185886, the simple increase in the source voltage of each memory cell as compared with that of the peripheral circuit will yield an increase in current consumption of the memory cell, thereby causing an increase in power consumption of the whole chip. Further, when the gate length of each MOSFET constituting the memory cell is made long to enhance a device withstand voltage, an exclusively-possessed area of the memory cell will increase.
An object of the present invention is to provide a technology capable of improving a noise margin and making a read rate fast in a static RAM equipped with memory cells comprising MOSFETs.
Another object of the present invention is to provide a technology capable of effectively reducing power consumption and decreasing an exclusively-possessed area of each of memory cells in a static RAM equipped with the memory cells comprising MOSFETs.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described as follows:
In a semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, an operating voltage of each memory cell is set higher than an operating voltage of a peripheral circuit, a threshold voltage of each MOS transistor included in the memory cell is set higher than a threshold voltage of each MOS transistor included in the peripheral circuit, a gate insulating film for the MOS transistors included in the memory cell is formed so as to be regarded as thicker than a gate insulating film for the MOS transistors included in the peripheral circuit in the case of conversion to an insulating film of the same material, and a selection level for each word line and a precharge level for each bit line pair are set identical to the level of the operating voltage of the peripheral circuit.
According to the above means, since the operating voltage of the memory cell is high and the threshold voltage of each MOSFET constituting the memory cell is high, a leak current of the memory cell can be reduced and power consumption can be diminished. Further, since the operating voltage of the peripheral circuit is lower than the operating voltage of the memory cell, an operating speed of the peripheral circuit can be made fast, and read and write rates can be enhanced as the whole semiconductor memory device.
Here, preferably, the ratio between a gate width and a gate length of each transmission MOS transistor included in the memory cell is set so as to be identical to or larger than the ratio between a gate width and a gate length of each of N channel MOS transistors included in a first CMOS inverter and a second CMOS inverter. Thus, a current read from each memory cell is increased to allow the read rate to make fast without degrading stability of the memory cell.
Another invention of the present application provides a semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, wherein an operating voltage of each memory cell and an operating voltage of each of driver circuits for driving each of word lines to a select level are set higher than an operating voltage of a peripheral circuit other than the driver circuits, a threshold voltage of each MOS transistor included in the memory cell is set higher than a threshold voltage of each MOS transistor included in the peripheral circuit other than the driver circuits, a gate insulating film for the MOS transistors included in the memory cell is formed so as to be regarded as thicker than a gate insulating film for the MOS transistors included in the peripheral circuit in the case of conversion to an insulating film of the same material, and a selection level for the word line is set higher than the level of the operating voltage of the peripheral circuit.
According to the above means, since the operating voltage of the memory cell is high and the threshold voltage of each MOSFET constituting the memory cell is high, a leak current of the memory-cell can be reduced and power consumption can be diminished. Further, since the operating voltage of the peripheral circuit is lower than the operating voltage of the memory cell, an operating speed of the peripheral circuit can be made fast, and read and write rates can be enhanced as the whole semiconductor memory device. Since the word-line selection level is high, a read current can be significantly increased although stability of the memory cell is slightly degraded as compared with the invention according to claim 1, and hence the read rate can be made fast.
Here, preferably, the ratio between a gate width and a gate length of each transmission MOS transistor included in the memory cell is set so as to be identical to or smaller than the ratio between a gate width and a gate length of each of N channel MOS transistors included in a first CMOS inverter and a second CMOS inverter. Thus, a static noise margin of each memory cell is increased to make it possible to enhance the stability of the memory cell without lowering the read rate.